Fuse elements are widely used in semiconductor memory devices to provide nonvolatile designations of active modes therein. For example, as described in U.S. Pat. No. 5,469,388 entitled Row Redundancy Circuit Suitable for High Density Semiconductor Memory Devices, assigned to the assignee of the present application, fuse circuits can be programmed to, among other things, substitute a spare cell array word line for a defective word line in a normal cell array. A fuse circuit can also be programmed so that when a defective word line is addressed, the fuse circuit activates a word line in a spare cell array and also activates a redundancy signal line. Preferably, when a fuse circuit has been programmed to allow a spare word line to replace a defective word line in a normal cell array, the fuses in the fuse circuit are blown to provide nonvolatile detection of the address signal of the defective word line.
Typical methods of blowing fuses include (i) irradiation by a laser at a surface of an exposed integrated circuit chip, prior to packaging of the chip, and (ii) application of a high level current through a fuse element. However, because the former method is generally only capable of being used at the wafer or chip stage when the fuse element can be exposed to light, it is less advantageous than the current application method which can be used after final packaging of the integrated circuit chip by applying preselected signals to the pins of the packaged chip.
Referring now to FIG. 1, a prior art circuit for generating option changing signals which can be used, for example, to detect addresses of defective lines and select a redundant decoder of a memory circuit, will be described. As will be understood by those skilled in the art, the fuse circuits of FIG. 1 may be programmed in advance to recognize addresses of defective lines and select redundancy decoders by selectively disconnecting (i.e., "blowing") fuses therein and causing the generation of option changing signals based on the disconnected fuses. As described more fully below, the first internal option changing signal generator 300 of FIG. 1 can be programmed to generate a "high" (i.e., logic 1) first internal option changing signal by blowing a fuse 49 therein in response to predetermined first and second external input signals. Similarly, the second internal option changing signal generator 301 of FIG. 1 can also be programmed, in parallel with the first generator 300, to generate a "high" second internal option changing signal by blowing a fuse 49 therein in response to third and fourth external input signals. As described herein, the construction of Blocks 100 and 101 correspond to the circuit of FIG. 3A; the construction of Blocks 200 and 201 correspond to the circuit of FIG. 3B; and the construction of Blocks 300 and 301 correspond to the circuit of FIG. 3C. In the circuit of FIG. 3A, three inverters (2, 10 and 11), three NAND gates (3, 6 and 9) and four NOR gates (4, 5, 7 and 8) are provided, as illustrated. In the circuit of FIG. 3B, two NAND gates (20 and 28), eight inverters (21-27 and 29) and a resistor 30 and capacitor 31 are provided. Finally, in the circuit of FIG. 3C, two NMOSFETS (50 and 43), three inverters (44, 46-47), two capacitors (41 and 45), a fuse 49 and resistor 42 are provided, as illustrated.
In particular, programming of the first option changing signal generator 300 can be performed by applying a preselected nine-bit wide first external input signal (e.g., 000011100) to pins 1-9 of the first fuse signal generator 100 to generate a "high" (e.g., logic 1) output. This output is then provided in combination with a second external input signal to the input of a two-input NAND gate 20 of the second fuse signal generator 200. This generates a "high" second fuse signal at the output of the second fuse signal generator 200. The second fuse signal is then provided as an input to the gate electrode of an NMOS transistor 50 within an input block 40, as illustrated by FIG. 3C. The application of a "high" signal to the gate of the NMOS transistor causes the fuse 49 to blow in response to a high current level, supplied by the power supply (VDD). The occurrence of a blown fuse 49 causes the input to an inverter 44 to be pulled "low" and the generation of a "high" first internal option changing signal at the output of Block 300. Because the step of blowing the fuse 49 generally cannot be reversed, the first internal option changing signal can be used to provide a nonvolatile designation of an active mode of an integrated circuit, such as a memory circuit as described above. Similar programming steps can also be performed to generate a second internal option changing signal in response to third and fourth external input signals, simultaneously with the steps to generate the first internal option changing signal.
Unfortunately, the yield of integrated circuits embodying fuses, for providing nonvolatile designations of active modes therein, can be adversely affected by spurious programming signals and noise signals if these signals inadvertently cause a "high" level signal at the gate of the NMOS transistor 50, resulting in a blown fuse 49. Accordingly, these exists a need to more reliably protect against noise and spurious programming signals which might adversely cause a fuse to be inadvertently blown.